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Introduction

The ``DPA Contest'' is organised by the VLSI research group from the COMELEC department of the Télécom ParisTech french University. It has been officially opened at the occasion of the CHES'08 conference (Sunday 10th to Wednesday 13rd August 2008). Some power consumption traces have been made available, in order to allow the hardware security community to check their attack algorithms against large amounts of freely available traces.

The goal of this initiative is to make it possible for researchers to compare in an objective manner their different attack algorithms. As this was impossible yesterday, because traces made by different laboratories are too different (acquisition platform sensitivity, cryptographic algorithm implementation, board's noise, ...), the www.dpacontest.org is an initiative towards an international benchmarking reference. Also, we expect significant advances or even breakthroughs to be stimulated by this peer-reviewed contest.

Contest Context

As the field of the hardware security is very large (refer for instance to this document from the Common Criteria), we will focus this contest on a specific class of attacks, made on a unique cryptographic algorithm and for a unique implementation:

Acquisition Platform

The traces have been measured by an home-made acquisition platform, described extensively in Appendix A of the PhD thesis of Sylvain GUILLEY. This acquisition platform belongs to TELECOM ParisTech.

Other publicly described side-channel acquisition platforms are listed below:

The OpenSCA project from University of Bristol, UK, provides with sample traces along with demo attack softwares.


Disclaimer: the data and code provided by www.dpacontest.org apply to the evaluation of academic, unprotected and whitebox cryptographic implementations. The goal of this contest is definitely not to encourage piracy on whatsoever commercial hardware; instead, it aims at enhancing the state-of-the-art of ``hardware security'' against observation attacks. This approach has proven to be efficient in cryptography: the AES, the SHA-3 or the eSTREAM contests are emblematic in this respect. We wish to apply this model at the hardware level. The advances in this field also help prepare the security challenges to be met with the advent of forthcoming nano-technologies.


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