Introduction
The DPA Contest v2 is organized by the VLSI research group from the COMELEC department of the Télécom ParisTech french University. Its is a continuation of the first version whose results were announced during the CHES09 conference.
The goal of this initiative is to make it possible for researchers to compare in an objective manner their different attack algorithms. As this was impossible yesterday, because traces made by different laboratories are too different (acquisition platform sensitivity, cryptographic algorithm implementation, board's noise...), the DPA contest is an initiative towards an international benchmarking reference. Also, we expect significant advances or even breakthroughs to be stimulated by this peer-reviewed contest.
The key points of this second version of the DPA contest are summarized below. The full rules are available on the Rules page.
- The class of attacks we consider is Differential Power Analysis like attacks (SPA, DPA, CPA, MIA, and any variant).
- We have switched to AES-128.
- We consider known-message and profiled attacks.
- We introduced different metrics to evaluate the efficiency of the submitted attacks: partial success rate, partial guessing entropy, global success rate, execution time and memory footprint.
- The acquisitions have been performed on a SASEBO GII board and we provide the full design used for the acquisitions.
Latest news
- 23/02/2010: A new release of the tools (attack wrapper and metrics computation tool) and a Python version of the reference attack are available to download. This release solves some portability issues and allows the use of traces from the disk instead of the network.
Older news are available on the News page.
Organizers and sponsors
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SASEBO GII special offer
The side channel attack standard evaluation board SASEBO-GII newly developed by AIST (National Institute of Advanced Industrial Science and Technology) will used for the third DPA contest.
The SASEBO project has been started by AIST and Tohoku University as a research project funded by METI (Ministry of Economy, Trade and Industry, Japan).
The third contest will be using an actual AES circuit implemented on the Virtex-5 FPGA. Academic research institutes who participate in the second DPA contest can receive the free SASEBO-GII board sponsored by CRI (Cryptography Research Inc.) for the third contest. The free distribution will be started June 2010. Participants of the third contest from industry can obtain the board as a commercial product from TED (Tokyo Electron Device). The AES circuit and support materials jointly-developed by AIST and Tohoku University will be continually uploaded on the DPA contest website.
Disclamer
The data and code provided by www.dpacontest.org apply to the evaluation of academic, unprotected and whitebox cryptographic implementations. The goal of this contest is definitely not to encourage piracy on whatsoever commercial hardware; instead, it aims at enhancing the state-of-the-art of ``hardware security'' against observation attacks. This approach has proved to be efficient in cryptography: the AES, the SHA-3 or the eSTREAM contests are emblematic in this respect. We wish to apply this model at the hardware level. The advances in this field also help prepare the security challenges to be met with the advent of forthcoming nano-technologies.