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Introduction

The DPA Contest v2 was organized by the VLSI research group from the COMELEC department of the Télécom ParisTech french University. Its is a continuation of the first version whose results were announced during the CHES09 conference.

The goal of this initiative is to make it possible for researchers to compare in an objective manner their different attack algorithms. As this was impossible yesterday, because traces made by different laboratories are too different (acquisition platform sensitivity, cryptographic algorithm implementation, board's noise...), the DPA contest is an initiative towards an international benchmarking reference. Also, we expect significant advances or even breakthroughs to be stimulated by this peer-reviewed contest.

The key points of this second version of the DPA contest are summarized below. The full rules are available on the Rules page.

How to participate?

A step-by-step guide is available on the Participate page, which describes how to install our tools, how to launch them on the reference attack, how to develop and test your own attack and how to submit it for evaluation.

After the presentation of the preliminary results during CHES 2010 workshop, the full results were announced at COSADE 2011 (slides are available here).

Although the official deadline for submission to the DPA contest v2 has passed, you can continue to submit your attack to the contest. It will be evaluated as quickly as possible and the results will be published on the Hall of Fame.

Latest news

You can follow the latest news from the DPA contest by following our official Twitter account or the RSS feed.

A press release has been published by the Institut Télécom about the DPA contest.

Organizers and sponsors

Institut Mines-Télécom logo Télécom ParisTech logo Centre National de la Recherche logo

SASEBO GII special offer

The side channel attack standard evaluation board SASEBO-GII newly developed by AIST (National Institute of Advanced Industrial Science and Technology) will used for the third DPA contest.

The SASEBO project has been started by AIST and Tohoku University as a research project funded by METI (Ministry of Economy, Trade and Industry, Japan).

The third contest will be using an actual AES circuit implemented on the Virtex-5 FPGA. Academic research institutes who participate in the second DPA contest can receive the free SASEBO-GII board sponsored by CRI (Cryptography Research Inc.) for the third contest. The free distribution will be started June 2010. Participants of the third contest from industry can obtain the board as a commercial product from TED (Tokyo Electron Device). The AES circuit and support materials jointly-developed by AIST and Tohoku University will be continually uploaded on the DPA contest website.

This special offer has expired since January 2012.

Cryptography Research Inc. logo

Disclamer

The data and code provided by www.dpacontest.org apply to the evaluation of academic, unprotected and whitebox cryptographic implementations. The goal of this contest is definitely not to encourage piracy on whatsoever commercial hardware; instead, it aims at enhancing the state-of-the-art of ``hardware security'' against observation attacks. This approach has proved to be efficient in cryptography: the AES, the SHA-3 or the eSTREAM contests are emblematic in this respect. We wish to apply this model at the hardware level. The advances in this field also help prepare the security challenges to be met with the advent of forthcoming nano-technologies.